The disclosure is generally related to a semiconductor device, and specifically to a semiconductor device having a trench gate structure.
Japanese Patent Application Publication No. 2013-065774 (Prior art document 1) discloses a metal oxide semiconductor (MOS) transistor including trenches. The MOS transistor includes the trenches 20 which penetrate an N-type source region 13 and a P-type base region 12 and terminate in an N-type drift region 11. A gate electrode 26 is provided in each trench 20 with an insulating film 25 provided between the gate electrode 26 and a side wall of the trench 20. With the reduction of the trench width and the intervals between adjacent trenches, the number of gate electrodes in a unit area increases in the trench MOS transistor. The trench MOS transistor achieves reduction of on-resistance.
In the MOS transistor disclosed in the prior art document 1, a depletion layer spreads from a PN interface between the N-type region 11 and the P-type region 12 when the transistor is off. Since the depletion layer does not spread beyond the N-type region 11, an electric field concentrates near a corner of a bottom portion of each trench 20. Accordingly, a counter electrode with a floating potential or a potential electrically connected to a source electrode is provided below the gate electrode to suppress electric field concentration near the corner of the bottom portion of the trench 20.